Frequency Division and Counting

1. Frequency DivisionIn the Sequential Logic tutorials we saw how D-type Flip-Flop´s work and how they can beconnected together to form a Data Latch. Another useful feature of the D-type Flip-Flop is as abinary divider, for Frequency Division or as a "divide-by-2" counter. Here the inverted outputterminal Q (NOT-Q) is connected directly back to the Data input terminal D giving the device"feedback" as shown below.Divide-by-2 CounterIt can be seen from the frequency waveforms above, that by "feeding back" the output from Q tothe input terminal D, the output pulses at Q have a frequency that are exactly one half ( f÷2 ) thatof the input clock frequency. In other words the circuit produces Frequency Division as it nowdivides the input frequency by a factor of two (an octave). This then produces a type of countercalled a "ripple counter" and in ripple counters, the clock pulse triggers the first flip-flop whoseoutput triggers the second flip-flop, which inturn triggers the third flip-flop and so on through thechain.Toggle Flip-FlopAnother type of device that can be used for frequency division is the T-type or Toggle flip-flop.With a slight modification to a standard JK flip-flop, we can construct a new type of flip-flopcalled a Toggle flip-flop were the two inputs J and k of a JK flip-flop are connected togetherresulting in a device with only two inputs, the "Toggle" input itself and the controlling "Clock"input. The name "Toggle flip-flop" indicates the fact that the flip-flop has the ability to toggle

2. between its two states, the "toggle state" and the "memory state". Since there are only two states,a T-type flip-flop is ideal for use in frequency division and counter design.Binary ripple counters can be built using "Toggle" or "T-type flip-flops" by connecting theoutput of one to the clock input of the next. Toggle flip-flops are ideal for building ripplecounters as it toggles from one state to the next, (HIGH to LOW or LOW to HIGH) at everyclock cycle so simple frequency divider and ripple counter circuits can easily be constructedusing standard T-type flip-flop circuits.If we connect together in series, two T-type flip-flops the initial input frequency will be"divided-by-two" by the first flip-flop ( f÷2 ) and then "divided-by-two" again by the second flip-flop ( f÷2 )÷2, giving an output frequency which has effectively been divided four times, then itsoutput frequency becomes one quarter value (25%) of the original clock frequency, ( f÷4 ). Eachtime we add another toggle or "T-type" flip-flop the output clock frequency is halved or divided-by-2 again and so on, giving an output frequency of 2nwhere "n" is the number of flip-flops usedin the sequence.Then the Toggle or T-type flip-flop is an edge triggered divide-by-2 device based upon thestandard JK-type flip flop and which is triggered on the rising edge of the clock signal. The resultis that each bit moves right by one flip-flop. All the flip-flops can be asynchronously reset andcan be triggered to switch on either the leading or trailing edge of the input clock signal makingit ideal for Frequency Division.Frequency Division using Toggle Flip-flopsThis type of counter circuit used for frequency division is commonly known as anAsynchronous 3-bit Binary Counter as the output on QA to QC, which is 3 bits wide, is abinary count from 0 to 7 for each clock pulse. In an asynchronous counter, the clock is appliedonly to the first stage with the output of one flip-flop stage providing the clocking signal for thenext flip-flop stage and subsequent.

3. This arrangement is commonly known as Asynchronous as each clocking event occursindependently as all the bits in the counter do not all change at the same time. As the countercounts sequentially in an upwards direction from 0 to 7. This type of counter is also known as an"up" or "forward" counter (CTU) or a "3-bit Asynchronous Up Counter". The three-bitasynchronous counter shown is typical and uses flip-flops in the toggle mode. Asynchronous"Down" counters (CTD) are also available.Truth Table for a 3-bit Asynchronous Up CounterClockCycleOutput bit PatternQC QB QA0 0 0 01 0 0 12 0 1 03 0 1 14 1 0 05 1 0 16 1 1 07 1 1 1Then by cascading together D-type or Toggle Flip-Flops we can produce divide-by-2, 4, 8 etc,asynchronous counter circuits which divide the clock frequency 2, 4 or 8 times.CountersThen a counter is a specialised register or pattern generator that produces a specified outputpattern or sequence of binary values (or states) upon the application of an input pulse called the"Clock". The clock is actually used for data in these applications. Typically, counters are logiccircuits than can increment or decrement a count by one but when used as asynchronous divide-by-n counters they are able to divide these input pulses producing a clock division signal.Counters are formed by connecting flip-flops together and any number of flip-flops can beconnected or "cascaded" together to form a "divide-by-n" binary counter where "n" is the numberof counter stages used and which is called the Modulus. The modulus or simply "MOD" of acounter is the number of output states the counter goes through before returning itself back tozero, ie, one complete cycle. A counter with three flip-flops like the circuit above will countfrom 0 to 7 ie, 2n-1. It has eight different output states representing the decimal numbers 0 to 7and is called a Modulo-8 or MOD-8 counter. A counter with four flip-flops will count from 0 to15 and is therefore called a Modulo-16 counter and so on.An example of this is given as.3-bit Binary Counter = 23= 8 (modulo-8 or MOD-8)

4. 4-bit Binary Counter = 24= 16 (modulo-16 or MOD-16)8-bit Binary Counter = 28= 256 (modulo-256 or MOD-256)The Modulo number can be increased by adding more flip-flops to the counter and cascading is amethod of achieving higher modulus counters. Then the modulo or MOD number can simply bewritten as: MOD number = 2n4-bit Modulo-16 CounterMulti-bit asynchronous counters connected in this manner are also called "Ripple Counters" orripple dividers because the change of state at each stage appears to "ripple" itself through thecounter from the LSB output to its MSB output connection. Ripple counters are available instandard IC form, from the 74LS393 Dual 4-bit counter to the 74HC4060, which is a 14-bitripple counter with its own built in clock oscillator and produce excellent frequency division ofthe fundamental frequency.Frequency Division Summary

5. For frequency division, toggle mode flip-flops are used in a chain as a divide by two counter.One flip-flop will divide the clock, ƒin by 2, two flip-flops will divide ƒin by 4 (and so on). Onebenefit of using toggle flip-flops for frequency division is that the output at any point has anexact 50% duty cycle.The final output clock signal will have a frequency value equal to the input clock frequencydivided by the MOD number of the counter. Such circuits are known as "divide-by-n" counters.Counters can be formed by connecting individual flip-flops together and are classified accordingto the way they are clocked. In Asynchronous counters, (ripple counter) the first flip-flop isclocked by the external clock pulse and then each successive flip-flop is clocked by the output ofthe preceding flip-flop. In Synchronous counters, the clock input is connected to all of the flip-flop so that they are clocked simultaneously.In the next tutorial we will look at Asynchronous counters, and see that the main characteristic ofan asynchronous counter is that each flip-flop in the chain derives its own clock from theprevious flip-flop and is therefore independent of the input clock.Asynchronous CounterIn the previous tutorial we saw that an Asynchronous counter can have 2n-1 possible countingstates e.g. MOD-16 for a 4-bit counter, (0-15) making it ideal for use in Frequency Division. Butit is also possible to use the basic asynchronous counter to construct special counters withcounting states less than their maximum output number by forcing the counter to reset itself tozero at a pre-determined value producing a type of asynchronous counter that has truncatedsequences. Then an n-bit counter that counts up to its maximum modulus (2n) is called a fullsequence counter and a n-bit counter whose modulus is less than the maximum possible is calleda truncated counter.But why would we want to create an asynchronous truncated counter that is not a MOD-4,MOD-8, or some other modulus that is equal to the power of two. The answer is that we can byusing combinational logic to take advantage of the asynchronous inputs on the flip-flop. If wetake the modulo-16 asynchronous counter and modified it with additional logic gates it can bemade to give a decade (divide-by-10) counter output for use in standard decimal counting andarithmetic circuits.Such counters are generally referred to as Decade Counters. A decade counter requires resettingto zero when the output count reaches the decimal value of 10, ie. when DCBA = 1010 and to dothis we need to feed this condition back to the reset input. A counter with a count sequence frombinary "0000" (BCD = "0") through to "1001" (BCD = "9") is generally referred to as a BCDbinary-coded-decimal counter because its ten state sequence is that of a BCD code but binarydecade counters are more common.Asynchronous Decade Counter

6. This type of asynchronous counter counts upwards on each leading edge of the input clock signalstarting from "0000" until it reaches an output "1010" (decimal 10). Both outputs QB and QD arenow equal to logic "1" and the output from the NAND gate changes state from logic "1" to alogic "0" level and whose output is also connected to the CLEAR (CLR) inputs of all the J-KFlip-flops. This causes all of the Q outputs to be reset back to binary "0000" on the count of 10.Once QB and QD are both equal to logic "0" the output of the NAND gate returns back to a logiclevel "1" and the counter restarts again from "0000". We now have a decade or Modulo-10counter.Decade Counter Truth TableClockCountOutput bit Pattern DecimalValueQD QC QB QA1 0 0 0 0 02 0 0 0 1 13 0 0 1 0 24 0 0 1 1 35 0 1 0 0 46 0 1 0 1 57 0 1 1 0 68 0 1 1 1 79 1 0 0 0 810 1 0 0 1 911 Counter Resets its Outputs back to ZeroDecade Counter Timing Diagram

7. Using the same idea of truncating counter output sequences, the above circuit could easily beadapted to other counting cycles be simply changing the connections to the AND gate. Forexample, a scale-of-twelve (modulo-12) can easily be made by simply taking the inputs to theAND gate from the outputs at "QC" and "QD", noting that the binary equivalent of 12 is "1100"and that output "QA" is the least significant bit (LSB). Since the maximum modulus that can beimplemented with n flip-flops is 2n, this means that when you are designing truncated countersyou should determine the lowest power of two that is greater than or equal to your desiredmodulus. For example, lets say you wish to count from 0 to 39, or mod-40. Then the highestnumber of flip-flops required would be six, n = 6 giving a maximum MOD of 64 as five flip-flops would only equal MOD-32.Then suppose we wanted to build a "divide-by-128"counter for frequency division we would need to cascadeseven flip-flops since 128 = 27. Using dual flip-flopssuch as the 74LS74 we would still need four ICs tocomplete the circuit. One easy alternative method wouldbe to use two TTL 7493s as 4-bit ripplecounter/dividers. Since 128 = 16 x 8, one 7493 could beconfigured as a "divide-by-16" counter and the other as a"divide-by-8" counter. The two ICs would be cascadedtogether to form a "divide-by-128" frequency divider as shown.Of course standard IC asynchronous counters are available such as the TTL 74LS90programmable ripple counter/divider which can be configured as a divide-by-2, divide-by-5 orany combination of both. The 74LS390 is a very flexible dual decade driver IC with a large

8. number of "divide-by" combinations available ranging form divide-by-2, 4, 5, 10, 20, 25, 50, and100.Frequency DividersThis ability of the ripple counter to truncate sequences to produce a "divide-by-n" output meansthat counters and especially ripple counters, can be used as frequency dividers to reduce a highclock frequency down to a more usable value for use in digital clocks and timing applications.For example, assume we require an accurate 1Hz timing signal to operate a digital clock. Wecould quite easily produce a 1Hz square wave signal from a standard 555 timer chip but themanufacturers data sheet tells us that it has a typical 1-2% timing error depending upon themanufacturer, and at low frequencies a 2% error at 1Hz is not good. However the data sheet alsotells us that the maximum operating frequency of the 555 timer is about 300kHz and a 2% errorat this high frequency would be acceptable. So by choosing a higher timing frequency of say262.144kHz and an 18-bit ripple (Modulo-18) counter we can make a precision 1Hz timingsignal as shown below.Simple 1Hz timing signal using an 18-bit ripple counter/divider.This is of course a very simple example of how to produce accurate frequencies, but by usinghigh frequency crystal oscillators and multi-bit frequency dividers, precision frequencygenerators can be produced for for a range of applications ranging from clocks or watches toevent timing and even electronic piano/synthesizer music applications.The main disadvantages with asynchronous counters are that there is a small delay between thearrival of the clock pulse and its output due to the internal circuitry of the gate. In asynchronouscircuits this delay is called the Propagation Delay (giving the asynchronous ripple counter thenickname of propagation counter) and in some cases can produce false output counts. In large bitripple counter circuits the delay of all the separate stages are added together to give a summeddelay at the end of the chain which is why asynchronous counters are generally not used for inhigh frequency counting circuits were large numbers of bits are involved.Also, the outputs from the counter do not have a fixed time relationship with each other and donot occur at the same time due to their clocking sequence. Then, the more flip-flops that areadded to an asynchronous counter chain the lower the maximum operating frequency becomes.To overcome the problem of propagation delay Synchronous Counters were developed.

9. Then to summarise:Asynchronous Counters can be made from Toggle or D-type flip-flops.They are called asynchronous counters because the clock input of the flip-flops are notall driven by the same clock signal.Each output in the chain depends on a change in state from the previous flip-flopsoutput.Asynchronous counters are sometimes called ripple counters because the data appears to"ripple" from the output of one flip-flop to the input of the next.They can be implemented using "divide-by-n" circuits.Truncated counters can produce any modulus number count.Disadvantages of Asynchronous Counters:An extra "re-synchronizing" output flip-flop may be required.To count a truncated sequence not equal to 2n, extra feedback logic is required.Counting a large number of bits, propagation delay by successive stages may becomeundesirably large.This delay gives them the nickname of "Propagation Counters".Counting errors at high clocking frequencies.Synchronous Counters are faster using the same clock signal for all flip-flops.In the next tutorial about Counters, we will look at the Synchronous Counter and see that themain characteristic of an synchronous counter is that the clock input of each flip-flop in the chainis connected to all of the flip-flops so that they are clocked simultaneously.Binary Synchronous CounterIn the previous Asynchronous binary counter tutorial, we saw that the output of one counterstage is connected directly to the clock input of the next counter stage and so on along the chain,and as a result the asynchronous counter suffers from what is known as "Propagation Delay".However, with the Synchronous Counter, the external clock signal is connected to the clockinput of EVERY individual flip-flop within the counter so that all of the flip-flops are clockedtogether simultaneously (in parallel) at the same time giving a fixed time relationship. In otherwords, changes in the output occur in "synchronization" with the clock signal. This results in allthe individual output bits changing state at exactly the same time in response to the commonclock signal with no ripple effect and therefore, no propagation delay.Binary 4-bit Synchronous Counter

10. It can be seen that the external clock pulses (pulses to be counted) are fed directly to each J-Kflip-flop in the counter chain and that both the J and K inputs are all tied together in toggle mode,but only in the first flip-flop, flip-flop A (LSB) are they connected HIGH, logic "1" allowing theflip-flop to toggle on every clock pulse. Then the synchronous counter follows a predeterminedsequence of states in response to the common clock signal, advancing one state for each pulse.The J and K inputs of flip-flop B are connected to the output "Q" of flip-flop A, but the J and Kinputs of flip-flops C and D are driven from AND gates which are also supplied with signalsfrom the input and output of the previous stage. If we enable each J-K flip-flop to toggle basedon whether or not all preceding flip-flop outputs (Q) are "HIGH" we can obtain the samecounting sequence as with the asynchronous circuit but without the ripple effect, since each flip-flop in this circuit will be clocked at exactly the same time. As there is no propagation delay insynchronous counters because all the counter stages are triggered in parallel the maximumoperating frequency of this type of counter is much higher than that of a similar asynchronouscounter.4-bit Synchronous Counter Waveform Timing Diagram.

11. Because this 4-bit synchronous counter counts sequentially on every clock pulse the resultingoutputs count upwards from 0 ( "0000" ) to 15 ( "1111" ). Therefore, this type of counter is alsoknown as a 4-bit Synchronous Up Counter.As synchronous counters are formed by connecting flip-flops together and any number of flip-flops can be connected or "cascaded" together to form a "divide-by-n" binary counter, themodulos or "MOD" number still applies as it does for asynchronous counters so a Decadecounter or BCD counter with counts from 0 to 2n-1 can be built along with truncated sequences.Decade 4-bit Synchronous CounterA 4-bit decade synchronous counter can also be built using synchronous binary counters toproduce a count sequence from 0 to 9. A standard binary counter can be converted to a decade(decimal 10) counter with the aid of some additional logic to implement the desired statesequence. After reaching the count of "1001", the counter recycles back to "0000". We now havea decade or Modulo-10 counter.Decade 4-bit Synchronous Counter

12. The additional AND gates detect when the sequence reaches "1001", (Binary 10) and causes flip-flop FF3 to toggle on the next clock pulse. Flip-flop FF0 toggles on every clock pulse. Thus, thecount starts over at "0000" producing a synchronous decade counter. We could quite easily re-arrange the additional AND gates to produce other counters such as a Mod-12 Up counter whichcounts 12 states from"0000" to "1011" (0 to 11) and then repeats making them suitable forclocks.Synchronous Counters use edge-triggered flip-flops that change states on either the "positive-edge" (rising edge) or the "negative-edge" (falling edge) of the clock pulse on the control inputresulting in one single count when the clock input changes state. Generally, synchronouscounters count on the rising-edge which is the low to high transition of the clock signal andasynchronous ripple counters count on the falling-edge which is the high to low transition of theclock signal.It may seem unusual that ripple counters use the falling-edge of the clock cycle to change state,but this makes it easier to link counters together because the most significant bit (MSB) of onecounter can drive the clock input of the next. This works because the next bit must change statewhen the previous bit changes from high to low - the point at which a carry must occur to thenext bit. Synchronous counters usually have a carry-out and a carry-in pin for linking counterstogether without introducing any propagation delays.Then to summarise:Synchronous Counters can be made from Toggle or D-type flip-flops.

13. They are called synchronous counters because the clock input of the flip-flops areclocked with the same clock signal.Due to the same clock pulse all outputs change simultaneously.Synchronous counters are also called parallel counters as the clock is fed in parallel toall flip-flops.Synchronous binary counters use both sequential and combinational logic elements.The memory section keeps track of the present state.The sequence of the count is controlled by combinational logic.Advantages of Synchronous Counters:Synchronous counters are easier to design.With all clock inputs wired together there is no inherent propagation delay.Overall faster operation may be achieved compared to Asynchronous counters.Count Down CounterAs well as counting "up" from zero and increase, or increment to some value, it issometimes necessary to count "down" from a predetermined value to zero and to producean output that activates when the zero count or other pre-set value is reached. This type ofcounter is normally referred to as a Down Counter, (CTD). In a binary or BCD downcounter, the count decreases by one for each external clock pulse from some preset value.Special dual purpose i.cs such as the TTL 74LS193 or CMOS CD4510 are 4-bit binaryUp or Down counters which have an additional input pin to select either the up or downcount mode.4-bit Count Down CounterIn the 4-bit counter above the output of each flip-flop changes state on the falling edge(1-to-0 transition) of the CLK input which is triggered by the Q output of the previousflip-flop, rather than by the Q output as in the up counter configuration. As a result, each

14. flip-flop will change state when the previous one changes from 0 to 1 at its output,instead of changing from 1 to 0.Bidirectional CounterBoth Synchronous and Asynchronous counters are capable of counting "Up" or counting"Down", but their is another more "Universal" type of counter that can count in bothdirections either Up or Down depending on the state of their input control pin and theseare known as Bidirectional Counters. Bidirectional counters, also known as Up/Downcounters, are capable of counting in either direction through any given count sequenceand they can be reversed at any point within their count sequence by using an additionalcontrol input as shown below.Synchronous 3-bit Up/Down Counter

15. The circuit above is of a simple 3-bit Up/Down synchronous counter using JK flip-flopsconfigured to operate as toggle or T-type flip-flops giving a maximum count of zero(000) to seven (111) and back to zero again. Then the 3-Bit counter advances upward insequence (0,1,2,3,4,5,6,7) or downwards in reverse sequence (7,6,5,4,3,2,1,0) butgenerally, bidirectional counters can be made to change their count direction at any pointin the counting sequence. An additional input determines the direction of the count, eitherUp or Down and the timing diagram gives an example of the counters operation as thisUp/Down input changes state.Nowadays, both up and down counters are incorporated into single IC that is fullyprogrammable to count in both an "Up" and a "Down" direction from any preset valueproducing a complete Bidirectional Counter chip. Common chips available are the74HC190 4-bit BCD decade Up/Down counter, the 74F569 is a fully synchronousUp/Down binary counter and the CMOS 4029 4-bit Synchronous Up/Down counter.

In the Sequential Logic tutorials we saw how D-type Flip-Flop´s work and how they can be connected together to form a Data Latch. Another useful feature of the D-type Flip-Flop is as a binary divider, for Frequency Division or as a “divide-by-2″ counter. Here the inverted output terminal Q (NOT-Q) is connected directly back to the Data input terminal D giving the device “feedback” as shown below.

It can be seen

from the frequency waveforms above, that by “feeding back” the output from Q to the input terminal D, the output pulses at Q have a frequency that are exactly one half ( f ÷ 2 ) that of the input clock frequency. In other words the circuit produces Frequency Division as it now divides the input frequency by a factor of two (an octave).
This then produces a type of counter called a “ripple counter” and in ripple counters, the clock pulse triggers the first flip-flop whose output triggers the second flip-flop, which in turn triggers the third flip-flop and so on through the chain producing a ripple effect (hence their name) of the timing signal as it passes through the chain.

Of the clock frequency using the appropriate number off FF's, this circuit could devide a frequency by any power of 2.Specifically, using N flip-flops would produce an output frequency from the last FF which is equal to 1/2N of the input frequency, this application of FF is referred to as frequency division. For frequency division, toggle mode flip-flops are used in a chain as a divide by two counter.

Counting Operation

In addition to functioning as a frequency divider, the circuit of figure 5-45 also operates as a Binary Counter. The clock is actually used for data transfer in these applications. Typically, counters are logic circuits that can increment or decrement a count by one but when used as asynchronous divide-by-n counters they are able to divide these input pulses producing a clock division signal.

Counters are formed by connecting flip-flops together and any number of flip-flops can be connected or “cascaded” together to form a “divide-by-n” binary counter where “n” is the number of counter stages used and which is called the Modulus. The modulus or simply “MOD” of a counter is the number of output states the counter goes through before returning itself back to zero, ie, one complete cycle.

Then a counter with three flip-flops like the circuit above will count from 0 to 7 ie, 2n-1. It has eight different output states representing the decimal numbers 0 to 7 and is called a Modulo-8 or MOD-8 counter. A counter with four flip-flops will count from 0 to 15 and is therefore called a Modulo-16 counter and so on.

 

On below, the circuit function as a binary counter in which the states of the FFs represent a binary number equivalent to the number of pulses thet have accured.

State Stansition Diagram

Figure 5-47 show how state of the FFs change with each applied clock pulse. Each circle represent one possible state as indicated by the binary number inside the circle.

The arrows connecting one circle to another show how one state changes to another as a clock pulse is applied.

To help describe, analyze, and design counters and other sequential circuit we will use state transition diagram.

MOD Number

The counter of figure 5-45 referred to as a MOD-8 counter, where the MOD number indicates the number of state in the counting sequence. The sequence of states would count in binary from 0000 to 1111 if fourth FF were added.

MOD-16 consist of toal of 16 states. The MOD number of the counter also indicates the frequency division obtained from the last FF.

References:

2001,Prentice Hall Digital systems principles and applications Edition 8th, Tocci;

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